Hardware Support for Sparse Matrix Computations
Members of the project team
Research objectives
Due to the importance of sparse matrix applications, research has been
conducted for hardware solutions to tackle problems that are inherent
to software controlled sparse data storage: fill-in, data movement, need
for memory management, indirect addressing, and hard-to-optimize
(obscured) code.
At the memory level, we propose architectures that support the storage
of sparse vectors and matrices. These memories are intended to be
embedded in existing processor systems or future general purpose
computing environments.
At the cache level, we discuss a few typical applications and extract
a set of basic sparse matrix computational primitives for further
discussion. These applications include sparse matrix vector multiply
and triangular solve.
It is argued that the basic operations in sparse matrix applications
are SpV-SpV (SpV: sparse vector, V: dense vector), SpV-V, and
V-V operations. Both update (X += Y) and inner products occur.
Although SpV-V and V-V operations can be executed efficiently on
existing computer systems, the often occuring SpV-SpV operations can
in general not very efficiently be implemented. For these operations,
hardware improvements at the cache level are proposed.
Collaborations
Within the ASCI research school and with
the APPARC consortium.
Timetable
Starting date: January 1993
Ending date: December 1995.
Intended results, deliverables
Improvements of processor (more specific: cache) architecture
for sparse matrix computations.
Recent Publications
- Arnold J. Niessen and Harry A.G. Wijshoff,
Memory Hardware Support for Sparse Computations,
in proceedings of the 27th Annual Hawaii International Conference
on System Sciences, Volume I, Januari 1994, pp 441-450,
edited by Trevor N. Mudge and Bruce D. Shriver.
- Arnold J. Niessen and Harry A.G. Wijshoff,
Cache Designs for Sparse Computations,
technical report, in preparation.
Last modified on July 2, 1996 by Lex Wolters.